The non-volatile electrically programmable and erasable memory devices sometimes referred to as Flash devices are explained in a variety of operations in the prior art. The section of this group called EEPROMs generally include two serially connected N-channel metal oxide semiconductor transistors, in which one of the transistors has an additional control gate that is floating and is sandwiched between the gate and the channel. This gate is used to store positive or negative charges which determine the state of the EEPROM. The other transistor is used for selection purposes. The charging of the floating gate is done by Fowler-Nordheim tunneling of electrons out of or into the floating gate. The oxide layer between the channel and the floating gate is around 100 .ANG. as reported in the prior art. These conventional flash devices require high voltages, are slow for programming and they occupy a large space due to the large capacitive coupling that is required between the floating gate and the control gate.
Another type of flash device as reported in (Intel flash patent) utilizes a single N-MOS transistor with a floating gate inserted between the control gate and the channel of the device. The oxide thickness for these type of flash cells is also around 100 .ANG.. The storing of the negative charge into the floating gate is achieved by injection of high energy electrons generated in the channel during charge transport between the source and the drain of the transistor. This requires a much lower voltage on the control gate but requires a larger source to drain current. The erase or removal of the negative charge is done exactly like the EEPROM cell with the exception that it should be performed under control to prevent over erasing of the cell, which leaves positive charge on the floating gate so that the transistor will remain "on" all the time and the cell selectivity will be lost. This type of flash cell which is smaller than the EEPROM cell and requires lower programming voltage but suffers from over erase and high current requirements. The high current requirements for this type of flash cell make it unsuitable for applications that use a battery as its power source. A further complication in this type of flash cell comes from the control of the erase voltage Vt. Since over erase has to be avoided for all the cells in the memory, the lower limit for the Vt of the erased cell can not be less than 0.5 V. Since all the cells do not erase the same way, there can be cells in the memory with Vt as high as 3.0 volts. A Vt of 3.0 V makes it impossible to operate the cell with 3 volts as a control voltage on the gate.